Boundary scan is a term used to describe circuitry typically built into discrete integrated circuits in accordance with the IEEE 1149.x standards. In general, a set of pins (known as the Test Access Port, or TAP) control a finite state machine internal to a boundary scan compliant integrated circuit (IC). Through electrical connections to the TAP pins of the IC, an external boundary scan controller is able to control the finite state machine within the IC.
Boundary scan is used primarily for two purposes: to test assembled circuit cards in order to locate manufacturing defects, and to program certain classes of components (comprising NOR FLASH, NAND FLASH, EEPROM, MRAM, and other types of programmable devices). Although it provides many valuable test and programming related functions, boundary scan has the disadvantage of being a relatively low speed test platform. Modern circuit design increasingly consists of high speed signals and large programmable devices, both of which present challenges. Many manufacturing and design defects cannot be detected at low speeds, and large programmable devices can require undesirably long periods of time to program.
Boundary scan consists of both serial and parallel elements. The finite state machine provides a means of shifting data in to and out from a boundary scan circuit serially. Serial input data contains binary values which control the function of pins on the associated IC(s) while boundary scan is active. For example, an output capable pin may be caused to drive a logic 0, a logic 1, or to be tri-stated. In another example, a bidirectional pin may be set to input mode. When the Update event occurs, the binary values from the serial input data take effect simultaneously. The states of output capable pins update in parallel when the Update event occurs. Serial output data contains a number of binary values, a portion of which corresponds to the logic states sensed by input capable pins at the previous capture event. Input capable pins are sampled in parallel when the Capture event occurs.
The IEEE 1149.x standards which define the operation of so-called compliant devices dictate that the Update and Capture events occur at different points within the state machine operation. The minimum time between Update and Capture events is 2.5 cycles of TCK, assuming 50% duty cycle for the IEEE 1149.x clock signal. The minimum time between two Update events (or between two Capture events) is roughly equal to the cycle time of TCK multiplied by the number of boundary scan cells within the boundary register(s) of the devices in a particular boundary scan chain. The maximum frequency that a particular boundary scan compliant device can operate at is defined by the manufacturer of that device. When a boundary scan controller is communicating with more than one boundary scan device, the maximum TCK frequency is determined by the individual lowest TCK frequency of any controlled boundary scan devices. Attempts to operate a particular device with a TCK faster than this maximum frequency violates timing, and correct device operation cannot be guaranteed or expected. These constraints impact test in four ways:                1. The time between the state change on an output signal and the next sense of an input signal will be a minimum of 2.5 TCK cycles. Propagation delays and other events which occur in less time than 2.5 TCK cycles cannot be observed accurately (Update to Capture timing limitation);        2. The time between subsequent state changes of output signals will in general be very long (Update to Update timing limitation);        3. The time between subsequent sense events will in general be very long (Capture to Capture timing limitation); and        4. The time between one sense event and the next state change will in general be very long (Capture to Update timing limitation).        
Numerous patents relating to methods to realize improved control over the timing of the Update and Capture events exist. U.S. Pat. No. 6,286,119 (the '119 patent) describes a method to enable testing of interconnect delay timing. The invention of the '119 patent requires the ability to implement a programmable delay following the Update event in order to allow control over the time between Update and Capture events. The invention of the '119 patent has the drawback of requiring additional signals beyond those defined by the standard IEEE 1149.x TAP port. U.S. Pat. No. 7,493,537 (the '537 patent) describes a method to provide extensions to the JTAG instruction set in order to enable testing of high speed IC to IC circuits. The invention of the '537 patent has the drawback of requiring modifications to the IEEE 1149.x standards in order to function. The '537 patent also requires an additional physical signal engaging with the TAP state machine. U.S. Patent Application No. 2013/0314102 (the '102 application) describes a method to add programmable timing circuitry within a boundary scan compliant device in order to facilitate timing related improvements. The invention of the '102 application has the drawback of requiring additional circuitry within boundary scan devices. It also has the drawback of requiring additional physical signals.
The IEEE 1149.x standards provide for the ability to connect multiple boundary scan devices together in a serial fashion (called boundary scan chains). In the most common topology, the first device in a chain has its TDI (Test Data In) pin configured in such a way as to enable it to be driven electrically by a boundary scan controller; the TDO (Test Data Out) pin from the first boundary scan device in a chain is configured in such a way that it is able to drive the TDI pin of the second device in the chain; the TDO pin from the boundary scan device at index N is configured in such a way that it is able to drive the TDI pin of the boundary scan device at index N+1, repeating until the final boundary scan device in the chain is reached; the TDO pin of the final boundary scan device in the chain is configured in such a way that it is able to electrically drive an input capable receiver at the boundary scan controller; the TMS pins of all boundary scan devices in the chain are configured in such a way that the boundary scan controller is able to drive all TMS pins simultaneously to the same logic level; generally, the boundary scan controller can drive all TMS pins within a given boundary scan chain either LO or HI simultaneously; the TCK pins of all boundary scan devices in the chain are configured in such a way that the boundary scan controller is able to drive all TCK pins simultaneously to the same logic level; generally, the boundary scan controller can drive all TCK pins within a given boundary scan chain either LO or HI simultaneously; the TRST pins of all boundary scan devices in the chain are configured in such a way that the boundary scan controller is able to drive all TRST pins simultaneously to the same logic level; generally, the boundary scan controller can drive all TRST pins within a given boundary scan chain either LO or HI simultaneously; the TRST pin is an optional pin per the 1149.x standards, which, in some topologies, may be continuously asserted HI, effectively removing the impact of the TRST pin from the state machines of impacted device(s).
Often, a boundary scan chain contains one or more boundary scan devices. However, a single-device chain is a valid boundary scan chain construct. A test access port, or TAP, is an IEEE defined term referring to the signals interfacing to the boundary scan state machine of a boundary scan device or boundary scan chain. The IEEE 1149.1 standard defines four required signals (TDI, TDO, TMS, and TCK) and one optional signal (TRST), which make up the TAP. The test data in, or TDI, signal is required in accordance with the IEEE 1149.1 standard. TDI is output from a boundary scan controller and input to a boundary scan device or chain. Instruction opcodes and input vectors are shifted in to a boundary scan device or chain via TDI. The test data out, or TDO, signal is required per the IEEE 1149.1 standard. TDO is input to a boundary scan controller and output from a boundary scan device or chain. Results from register read operations, as well as result vectors, are shifted out from a boundary scan device or chain via TDO. The test mode select, or TMS, signal is required per the IEEE 1149.1 standard. TMS is output from a boundary scan controller and input to a boundary scan device or chain. The test clock, or TCK, signal is required per the IEEE 1149.1 standard. TCK is output from a boundary scan controller and input to a boundary scan device or chain. TMS and TCK are used to control the state machines internal to a boundary scan device(s). The test reset, or TRST, signal is optional per the IEEE 1149.1 standard. TRST provides an asynchronous reset to the boundary scan state machine, machines of a boundary scan device, or boundary scan chain.
The IEEE 1149.7 standard (sometimes referred to as Compact JTAG) is similar to the IEEE 1149.1 standard. The IEEE 1149.7 standard defines two required signals (TMSC and TCKC) and three optional signals (TDI, TDO, and TRST). The test mode select compact, or TMSC, signal is required per the IEEE 1149.7 standard. TMSC operates in a flexible multiplexed fashion, allowing the functions of TDI, TDO, and TMS to be supported via a single bidirectional signal. When TDI functionality is active, the TMSC signal is an output from a controller and an input to a boundary scan device or chain. When TDO functionality is active, the TMSC signal is an input to a controller and an output from a boundary scan device or chain. When TMS functionality is active, the TMSC signal is an output from a controller and an input to a boundary scan device or chain. TCKC and the TMS portion of TMSC are used to control the state machines internal to a boundary scan device(s). The test dock compact, or TCKC, signal is required per the IEEE 1149.7 standard. TCKC is output from a boundary scan controller and input to a boundary scan device or chain. TCKC and the TMS portion of TMSC are used to control the state machines internal to a boundary scan device(s). The test data in, or TDI, signal is optional per the IEEE 1149.7 standard. TDI is output from a boundary scan controller and input to a boundary scan device or chain. Instruction opcodes and input vectors are shifted in to a boundary scan device or chain via TDI. The functions of TDI can be incorporated into the TMSC signal, making TDI optional. The test data out, or TDO, signal is optional per the IEEE 1149.7 standard. TDO is input to a boundary scan controller. And output from a boundary scan device or chain. Results from register read operations, as well as result vectors, are shifted out from a boundary scan device or chain via TDO. The functions of TDO can be incorporated into the TMSC signal, making TDO optional. The test reset, or TRST, signal is optional per the IEEE 1149.7 standard. TRST provides an asynchronous reset to the boundary scan state machine(s) of a boundary scan device or boundary scan chain.
There are numerous possible TAP port topologies for the various IEEE 1149.x standards. However, all TAP port topologies provide access to the state machine(s) of boundary scan device(s) or boundary scan chains. Provided that the TAP port topology matches the topology of a target boundary scan device or boundary scan chain, the end result is the same: a controller is able to control the state machine(s), shift opcodes or test vectors in to the device(s) or chain(s), and shift result data back from the device(s) or chain(s).
Multiple boundary scan chains can exist within a particular design. This is common practice, for a variety of reasons. One common practice is to group devices from a particular manufacturer together into a single boundary scan chain. This is done frequently to mitigate issues arising from any non-standard implementations of the 1149.x standard on the part of the relevant manufacturer. The JTAG port is frequently used for device programming and device emulation, as well as boundary scan based test. It is not uncommon for device programming or device emulation guidelines from the device manufacturer to require that a device be located in a restricted boundary scan chain. The restrictions on the chain may include, but are not limited to, limitations to the number of boundary scan devices in the chain and limitations to the vendor(s) of other boundary scan devices in the chain. The effective test vector pattern rate is roughly inversely related to the number of boundary scan cells in the chain. More devices in a chain leads to more cells, which leads to slower effective test vector pattern rates. By dividing a single large boundary scan chain into a number of shorter boundary scan chains, the effective test vector pattern rate can be increased. A single boundary scan chain can be formed by appropriately connecting two or more individual boundary scan chains. Thus, test hardware, software, or a combination of hardware and software, can be used to define the actual boundary scan topology.
The boundary scan state machine, as depicted in FIG. 5, includes a number of states. In accordance with the IEEE 1149.x standard, the state machine is navigated by asserting a binary value to the TMS signal(s), followed by applying a positive pulse to the IEEE 1149.x clock signal(s). Applying this to the boundary scan state machine in a manner currently utilized by existing boundary scan based test platforms yields the timing diagram shown in FIG. 6. Minor variations to the basic method of controlling the state machine exist within the IEEE 1149.x standard (including those defined by the 1149.7 standard), but these should not be construed as alternate methods of controlling the state machine. The states transited by the timing diagram in FIG. 6 should be transited in any functional instance of a boundary scan state machine controller.
The IEEE 1149.x standards are living documents, periodically updated. The 1149.7 standard defines a modified TAP port, consisting of a minimum of two pins: TCKC and TMSC. As described in the IEEE 1149 glossary, TCKC is roughly analogous to TCK as both are clocks. Either of these signals are referred to as the IEEE 1149.x clock signal throughout this document. In the IEEE 1149.7 standard, TMSC performs the functionality of TDI, TDO, and TMS signals through multiplexing. The IEEE 1149.7 standard makes use of the same state machine as its 1149.x predecessors. This continuity throughout the evolution of the 1149.x standards makes it possible for the testing system 100 described herein to inherently apply to 1149.7 compliant devices as well as all other IEEE 1149.x compliant devices.
FIG. 2 depicts a prior art design containing two independent boundary scan chains 103 and 104. The first chain includes test connector 101 physically connected to the TAP port of the first boundary scan chain, which includes first electrical component U1. The second chain includes test connector 102 physically connected to the TAP port of the second boundary scan chain, which includes second electrical component U2.
FIG. 3 depicts a single boundary scan chain 103 including two electrical components U1 and U2. The TMS, TCK, and TRST (an optional TAP signal) are connected in parallel to both electrical components U1 and U2 through a single test connector 101. The TDO of the upstream electrical component device U1 is connected to the TDI of a downstream electrical component U2. The boundary scan chain 103 has a single root TDI, at the first electrical component U1 in the boundary scan chain 103. The boundary scan chain 103 has a single root TDO, at the final electrical component U2 in the chain. The test connector 101 physically connects to the TAP port of the boundary scan chain 103.
FIG. 4 depicts a design containing two independent boundary scan chains 103 and 104. Test connector 101 physically connects to the TAP port of the first boundary scan chain 103. Test connector 102 physically connects to the TAP port of the second boundary scan chain 104. External connections to the test connectors 101 and 102 are shown connecting the TAP interfaces of the two boundary scan chains 103 and 104 into the same effective topology as the boundary scan chain 103 in FIG. 3.
Those skilled in the art of electrical design will recognize that it is possible to implement a number of methods in order to realize the ability to dynamically change the topology of a boundary scan chain or chains. For example, in FIG. 4, multiplexors or digital logic connected to the TAP interfaces of the electrical components U1 and U2 could be used dynamically reconfigure the two TAP ports, enabling the electrical components U1 and U2 to appear in independent chains, as well as a chain consisting of electrical components U1 and U2 in either forward or reverse order. These techniques have been used within the electronics industry.
FIG. 6 depicts a standard boundary scan timing diagram for a scenario containing two independent boundary scan chains 103 and 104. This diagram in FIG. 6 omits the TRST signal for simplicity. As the timing for the first boundary scan chain 103 and the second boundary scan chain 104 are identically, the timing diagram shown by FIG. 6 can be expanded indefinitely by adding additional blocks to accommodate additional boundary scan chains with no upper limit to the number of possible boundary scan chains. Most known boundary scan controllers cause their controlled boundary scan devices to traverse their respective state machines as depicted in FIG. 6. As the timing diagram shows, this boundary scan controller causes all boundary scan chains to traverse their respective state machines simultaneously.
As depicted in FIG. 6, all boundary scan chains change states effectively simultaneously. There may be slight deviations in the exact timing of the transitions of TMS and the IEEE 1149.x clock signal as a result of deviations in propagation delays internal to the electrical hardware responsible for asserting the associated signals, but the underlying intent is to keep all chains traversing their state machines synchronously.
At time t3, one Capture event occurs for all boundary scan chains. The input capable pins connected to all boundary scan chains capture their values effectively simultaneously. At time t1, one Update event occurs for all boundary scan chains. The values asserted by output capable pins connected to all boundary scan chains update effectively simultaneously. At time t2, a second Capture event occurs for all boundary scan chains. T2 occurs 2.5 IEEE 1149.7 clock signal cycles after t1. At time t4, a second Update event occurs for all boundary scan chains.
As depicted in FIG. 6, the period of time between t1 and t2 is defined by the IEEE 1149.x standards as requiring 2.5 cycles of the IEEE 1149.x clock signal (assuming 50% duty cycle for the IEEE 1149.x clock signal). Specifically, for a boundary scan chain in UPDATE-DR state, the falling edge of IEEE 1149.x clock signal causes the Update event within the relevant devices to occur. With TMS at a logic HI, the next rising edge of the IEEE 1149.x clock signal causes the boundary scan chain to enter SELECT-DR-SCAN state. A falling edge of the IEEE 1149.x clock signal is required in order for the state machine to proceed to the next state. With TMS at a logic LO, the next rising edge of the IEEE 1149.x clock causes the boundary scan chain to enter CAPTURE-DR state. A falling edge of the IEEE 1149.x clock is required in order for the state machine to proceed to the next state. With TMS at a logic LO, the next rising edge of the IEEE 1149.x clock signal causes the boundary scan chain to enter SHIFT-DR state. This causes the Capture event within the relevant devices to occur. The rising edge, falling edge, rising edge, falling edge, and rising edges described in this paragraph define the 2.5 IEEE 1149.x clock signal cycle minimum time between Update and Capture events referenced elsewhere in this document. As depicted in FIG. 6, binary values driven by output pins, referred to as Outputs_x in FIG. 6, are updated on the falling edge of the IEEE 1149.x clock signal while the device is in the UPDATE-DR state. As depicted in FIG. 6, binary values present at input pins, referred to as Inputs_x in FIG. 6, are captured on the rising edge of the IEEE 1149.x clock signal when the device enters the SHIFT-DR state.
The 2.5 TCK cycle minimum time between Update and Capture events represents a significant limitation for test purposes. One instance where this limitation limits test capability is delay timing. For a variety of reasons, knowledge of the amount of time it takes for a change in the value driven by one pin on a net to propagate to another pin on the same (or different) net is valuable information. Because logic level changes propagate at the speed of light in an environment void of resistive, inductive, and capacitive effects, the 2.5 TCK cycle minimum time between Update and Capture events precludes the ability to test delay timing. The propagation time is significantly smaller than the clock.
This background information is provided to reveal information believed by the applicant to be of possible relevance to the present invention. No admission is necessarily intended, nor should be construed, that any of the preceding information constitutes prior art against the present invention.